With this information, the tool can ignore these paths and concentrate on the real critical paths.
#SYNPLIFY PRO POWER REPORT PRO#
Provide all timing exceptions, such as false and multicycle paths, to the Synplify Pro tool. (Click this image to view a larger, more detailed version) If the setup time is too short, it is best to re-constrain the clocks so as to ensure that they are more related. You can check the setup time in the Clock Relationships table in the log file ( Fig 2 ). This may result in the worst-case setup time being very small (e.g. Warning: If the clocks are completely unrelated, it may require several clock periods before the clocks match up again. The tool then calculates the minimum setup time between the clocks in this case 10ns.
#SYNPLIFY PRO POWER REPORT SOFTWARE#
The Synplify software rolls the clocks forward until they match up again.
Instead, define all clocks in a constraint file (.sdc) and ensure that unrelated clocks are set in separate clock groups (when clocks are in the same group, the Synplify Pro tool works out the worst-case setup time for the clock-to-clock paths).Įxample: A timing diagram for two clocks that are in the same clock group is presented in Fig 1. The Fmax field on the front panel is fine for a quick run, but do not use it if you need maximum performance. This ensures that critical paths are squeezed as much as possible (see the discussions on Route constraint later in this tutorial for more information). For maximum performance, ensure that there is 10-15% negative slack on each critical clock. Under-constraining or over-constraining your design usually results in reduced performance. The following checklist describes the best practices to use when setting up your design.
Consequently, setting the correct goals in the Synplify Pro tool is an essential consideration with regard to obtaining the best results. Indeed, the Synplify Pro tool is timing-driven, which means that it simultaneously optimizes for area and performance, but it stops as soon as the timing constraints are met. Setting up your design correctly can result in huge performance increases or reduction in area (cost). This paper describes four preferred ways to set up your design and four methods of fine-tuning synthesis, all of which can be used together or independently. There are several ways to incrementally increase performance or reduce the area (utilization) of Altera devices using the Synplify Pro tool from Synplicity.
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